This invention relates to a semiconductor memory device capable of miniaturization and a fabrication method thereof. More particularly, in a dynamic random access memory (DRAM) suitable for high density integration, the present invention relates to a memory cell structure having a trench capacitor and a vertical transistor and a fabrication method thereof.
The integration density of DRAMs has been quadrupled in the past years or so, and a mass production system of a 4-Mbit DRAM has already been almost ready. This high density integration has been accomplished by miniaturizing a device size.
However, problems such as the drop of a signal-to-noise ratio (S/N) and signal inversion due to irradiation of .alpha.-particles have been manifested because of the drop of storage capacitance with miniaturization, as a result, it is a critical problem at present as to how to maintain device reliability.
Therefore, the following two types of memory cells have become predominant for DRAMS of 4-Mbit or more memory capacity as the memory cells that can increase the storage capacitance:
(1) A stacked capacitor memory cell wherein part of storage capacitance is stacked on a switching transistor or a field oxide; and PA1 (2) A trench type memory cell wherein a deep trench is formed in a substrate and a charge storage capacitor is formed on its sidewall. PA1 (1) A structure wherein a trench is formed in the substrate; and PA1 (2) A structure wherein a pillar is left in the substrate.
Fabrication of prototypes of 16-Mbit and 64-Mbit memory cells has been attempted by utilizing these three-dimensional memory cells in combination with a self-alignment process. If the memory cell area has to be reduced as has been necessary in the past, however, the memory cell area is as small as 0.5 .mu.m.sup.2 in a 256-Mbit memory cell. Accordingly, even if the memory structure described above is employed, it is not possible not only to secure sufficient storage capacitance but also to reduce the memory cell area. DRAMs include a capacitor for storing charge, a bit line for supplying the charge to the capacitor and a word line for controlling the flow of the charge, that extends along a channel area, as the minimum unit.
In conventional DRAMs, the charge storage capacitor and the word line have been fabricated planewise on a substrate, or only the capacitor has been formed three-dimensionally. Many memory cells having a structure wherein the word line or, in other words, the channel area in which the charge moves, is formed three-dimensionally have been proposed in order to further reduce the memory cell area. Some of their examples will be explained in detail with reference to FIGS. 1, 2 and 3 of the accompanying drawings.
The memory cell structures for forming the channel in the direction of depth of the substrate can be classified broadly into the following two groups:
FIG. 1 shows the example of the type 1 which is disclosed in JP-A-61-179571. The memory cell uses an epitaxial substrate including a layer 31 having a high impurity concentration and a layer 32 having a low impurity concentration, and the capacitor area and the channel area 36 are formed in the high impurity concentration layer and in the low impurity concentration layer, respectively. In accordance with the self-alignment process, one of the electrodes 34 of the charge storage capacitor is connected via region 35 electrically to the channel area, and a capacitor structure is accomplished immediately below the word line.
Here, reference numeral 33 denotes a capacitor insulation film, 37 is a diffusion layer as the bit line, 38 is an inter-layer insulation film and 39 is a word line electrode.
The memory cell shown in FIG. 2 is disclosed in JP-A-61-198772, which improves the memory cell described above. In this arrangement the channel area and the capacitor area are covered completely with the oxide film. In this memory cell the channel area 45 is covered with the oxide film and does not exist on the substrate side. Since the area to which the channel and one of the electrodes of the capacitor are to be connected is covered with the oxide film, too, a leakage current between the memory cells does not occur theoretically. The distance between the memory cells can be reduced drastically when this structure is employed.
The operation speed of the device can be improved because a wiring material having low resistance can be used for the bit lines 48, 49. Reference numeral 41 denotes a high concentration layer, 42 is a low concentration layer, 43 is a capacitor insulation film, 44 is one of the electrodes of the capacitor, 45 is a channel, 46 is a gate insulation film, 47 is an inter-layer insulation film and 50 is a word line electrode. In contrast with the memory cell structure described above, JP-A-1-248557 discloses a memory cell structure which utilizes a pillar formed on a silicon substrate and which is shown in FIG. 3. This prior art technology makes a trench in the substrate in three stages, and utilizes the sidewalls of the pillars formed at these stages as the channel 56, the capacitors 52, 53, 54 and the device-separation 55 from the upper surface in the order named, respectively.
As a result, each memory cell is isolated in self-alignment and this structure is optimal for reducing the distance between the memory cells. The word line 57 can utilize the portion which is left by self-alignment on the sidewall of the silicon pillar at the time of known anisotropic etching. This structure is characterized also in that if the gap between the silicon pillars in the longitudinal direction of the word line is smaller than twice the film thickness of the word line, etching of the word line can be made without any mask. Incidentally, reference numeral 51 denotes the semiconductor substrate, 55 is a high concentration impurity layer which is introduced in order to improve device isolation characteristics and has the same conductivity type as that of the substrate, 56 is the channel area and 58 is the bit line electrode.